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? semiconductor components industries, llc, 2006 january, 2006 ? rev. 4 1 publication order number: NBSG16M/d NBSG16M 2.5v/3.3vmultilevel input to cml clock/data receiver/driver/translator buffer description the NBSG16M is a differential current mode logic (cml) receiver/driver/translator buffer . the device is functionally equivalent to the ep16, lvep16, or sg16 devices with cml output structure and lower emi capabilities. inputs incorporate internal 50 termination resistors and accept lvnecl (negative ecl), lv pecl (positive ecl), lvttl, lvcmos, cml, or lvds. the cm l output structure contains internal 50 source termination resistor to v cc . the device generates 400 mv output amplitude with 50 receiver resistor to v cc . the v bb pin is internally generated voltage supply available to this device only. for all single ? ended input conditions, the unused complementary differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb output should be left open. features ? maximum input clock frequency > 10 ghz typical ? maximum input data rate > 10 gb/s typical ? 120 ps typical propagation delay ? 35 ps typical rise and fall times ? positive cml output with operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? negative cml output with rsnecl or necl inputs with operating range: v cc = 0 v with v ee = ? 2.375 v to ? 3.465 v ? cml output level; 400 mv peak ? to ? peak output with 50 receiver resistor to v cc ? 50 internal input and output termination resistors ? compatible with existing 2.5 v/3.3 v lvep, ep, lvel and sg devices ? v bb reference voltage output ? pb ? free packages are available *for additional marking information, refer to application note and8002/d. marking diagram* http://onsemi.com qfn ? 16 mn suffix case 485g 16 sg 16m alyw 1 ?? ?? 1 a = assembly location l = wafer lot y = year w = work week = pb ? free package see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information (note: microdot may be in either location)
NBSG16M http://onsemi.com 2 v cc nc v ee v ee v cc v bb v ee v ee v cc q q v cc vtd d d vtd 5678 16 15 14 13 12 11 10 9 1 2 3 4 NBSG16M exposed pad (ep) figure 1. qfn ? 16 pinout (top view) table 1. pin description pin name i/o description 1 ? internal 50 termination pin. see table 2. (note 3) 2 d lvds, cml, ecl, lvttl, lvcmos input inverted differential input (note 3) 3 d lvds, cml, ecl, lvttl, lvcmos input noninverted differential input. (note 3) 4 v td ? internal 50 termination pin. see table 2. (note 3) 5 v cc ? positive supply voltage. all v cc pins must be externally connected to power supply to guar- antee proper operation. 6 nc ? no connect (note 1) 7 v ee ? negative supply voltage. all v ee pins must be externally connected to power supply to guar- antee proper operation. 8 v ee ? negative supply voltage. all v ee pins must be externally connected to power supply to guar- antee proper operation. 9 v cc ? positive supply voltage. all v cc pins must be externally connected to power supply to guar- antee proper operation. 10 q cml output noninverted cml differential output with internal 50 source termination resistor. (note 2) 11 q cml output inverted cml differential output with internal 50 source termination resistor. (note 2) 12 v cc ? positive supply voltage. all v cc pins must be externally connected to power supply to guar- antee proper operation. 13 v ee ? negative supply voltage. all v ee pins must be externally connected to power supply to guar- antee proper operation. 14 v ee ? negative supply voltage. all v ee pins must be externally connected to power supply to guar- antee proper operation. 15 v bb ? internally generated ecl reference output voltage 16 v cc ? positive supply voltage. all v cc pins must be externally connected to power supply to guar- antee proper operation. ? ep ? exposed pad. the thermally exposed pad (ep) on package bottom (see case drawing) must be attached to a heat ? sinking conduit. 1. the nc pins are electrically connected to the die and must be left open. 2. cml outputs require 50 receiver termination resistor to v cc for proper operation. 3. in the differential configuration when the input termination pin (v td , v td ) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self ? oscillation.
NBSG16M http://onsemi.com 3 50 50 vtd d d vtd q q v bb v ee v cc 50 50 figure 2. logic diagram q q v cc 16 ma 50 50 figure 3. cml output structure v ee table 2. interfacing options interfacing options connections cml connect vtd and vtd to v cc lvds connect vtd and vtd together ac ? coupled bias vtd and vtd inputs within (v ihcmr ) common mode range rsecl, pecl, necl standard ecl termination techniques lvttl, lvcmos an external voltage should be applied to the unused complimentary differential input. nominal voltage 1.5 v for lvttl and v cc /2 for lvcmos inputs. table 3. attributes characteristics value esd protection human body model machine model charged device model > 1 kv > 100 v > 4 kv moisture sensitivity, indefinite time out of drypack (note 4) pb pkg pb ? free pkg qfn ? 16 level 1 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 145 meets or exceeds jedec spec eia/jesd78 ic latchup test 4. for additional moisture sensitivity information, refer to application note and8003/d.
NBSG16M http://onsemi.com 4 table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply v ee = 0 v 3.6 v v ee negative power supply v cc = 0 v ? 3.6 v v i positive input negative input v ee = 0 v v cc = 0 v v i v cc v i v ee 3.6 ? 3.6 v v v inpp differential input voltage |d ? d | v cc ? v ee 2.8 v v cc ? v ee < 2.8 v 2.8 |v cc ? v ee | v i in input current through r t (50 resistor) static surge 45 80 ma ma i out output current continuous surge 25 50 ma ma i bb v bb sink/source 1.0 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 5) 0 lfpm 500 lfpm qfn ? 16 qfn ? 16 42 35 c/w c/w jc thermal resistance (junction ? to ? case) 1s2p (note 5) qfn ? 16 4.0 c/w t sol wave solder pb pb ? free <2 to 3 sec @ 248 c <2 to 3 sec @ 260 c 265 265 c maximum ra tings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional oper ation is not im- plied, damage may occur and reliability may be affected. 5. jedec standard multilayer board ? 1s2p (1 signal, 2 power)
NBSG16M http://onsemi.com 5 table 5. dc characteristics, positive cml output v cc = 2.5 v; v ee = 0 v (note 6) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i cc positive power supply current 37 43 51 37 43 51 37 43 51 ma v oh output high voltage (note 7) v cc ? 40 v cc ? 10 v cc v cc ? 40 v cc ? 10 v cc v cc ? 40 v cc ? 10 v cc mv v ol output low voltage (note 6) v cc ? 400 v cc ? 330 v cc ? 400 v cc ? 330 v cc ? 400 v cc ? 330 mv v ih input high voltage (single ? ended) (note 8) v ee + 1.275 v cc ? 1.0* v cc v ee + 1.275 v cc ? 1.0* v cc v ee + 1..275 v cc ? 1.0* v cc v v il input low voltage (single ? ended) (note 8) v ee v cc ? 1.4* v ih ? 0.150 v ee v cc ? 1.4* v ih ? 0.150 v ee v cc ? 1.4* v ih ? 0.150 v v bb ecl reference voltage output 1075 1170 1265 1075 1170 1265 1075 1170 1265 mv v ihcmr input high voltage common mode range (note 8) (differential configuration) 1.2 2.5 1.2 2.5 1.2 2.5 v r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 r tout internal output termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@ v ih ) 60 100 60 100 60 100 a i il input low current (@ v il ) 25 50 25 50 25 50 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. input and output parameters vary 1:1 with v cc . v ee can vary +0.125 v to ? 0.965 v. 7. all loading with 50 to v cc . 8. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif feren- tial input signal. *typicals used for testing purposes.
NBSG16M http://onsemi.com 6 table 6. dc characteristics, positive cml output v cc = 3.3 v; v ee = 0 v (note 9) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i cc positive power supply current 37 43 51 37 43 51 37 43 51 ma v oh output high voltage (note 10) v cc ? 40 v cc ? 10 v cc v cc ? 40 v cc ? 10 v cc v cc ? 40 v cc ? 10 v cc mv v ol output low voltage (note 9) v cc ? 400 v cc ? 330 v cc ? 400 v cc ? 330 v cc ? 400 v cc ? 330 mv v ih input high voltage (single ? ended) (note 11) v ee + 1.275 v cc ? 1.0* v cc v ee + 1.275 v cc ? 1.0* v cc v ee + 1.275 v cc ? 1.0* v cc v v il input low voltage (single ? ended) (note 11) v ee v cc ? 1.4* v ih ? 0.150 v ee v cc ? 1.4* v ih ? 0.150 v ee v cc ? 1.4* v ih ? 0.150 v v bb ecl reference voltage output 1875 1970 2065 1875 1970 2065 1875 1970 2065 mv v ihcmr input high voltage common mode range (note 11) (differential configuration) 1.2 3.3 1.2 3.3 1.2 3.3 v r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 r tout internal output termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@ v ih ) 60 100 60 100 60 100 a i il input low current (@ v il ) 25 50 25 50 25 50 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. input and output parameters vary 1:1 with v cc . v ee can vary +0.925 v to ? 0.165 v. 10. all loading with 50 to v cc . 11. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif feren- tial input signal. *typicals used for testing purposes.
NBSG16M http://onsemi.com 7 table 7. dc characteristics, negative cml output v cc = 0 v; v ee = ? 3.465 to ? 2.375 v (note 12) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i cc positive power supply current 37 43 51 37 43 51 37 43 51 ma v oh output high voltage (note 13) v cc ? 40 v cc ? 10 v cc v cc ? 40 v cc ? 10 v cc v cc ? 40 v cc ? 10 v cc mv v ol output low voltage (note 12) v cc ? 400 v cc ? 330 v cc ? 400 v cc ? 330 v cc ? 400 v cc ? 330 mv v ih input high voltage (single ? ended) (note 13) v ee + 1.275 v cc ? 1.0* v cc v ee + 1.275 v cc ? 1.0* v cc v ee + 1.275 v cc ? 1.0* v cc v v il input low voltage (single ? ended) (note 13) v ee v cc ? 1.4* v ih ? 0.150 v ee v cc ? 1.4* v ih ? 0.150 v ee v cc ? 1.4* v ih ? 0.150 v v bb ecl reference voltage output ? 1425 ? 1330 ? 1235 ? 1425 ? 1330 ? 1235 ? 1425 ? 1330 ? 1235 mv v ihcmr input high voltage common mode range (note 14) (differential configuration) v ee +1.2 v cc v ee +1.2 v cc v ee +1.2 v cc v r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 r tout internal output termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@ v ih ) 60 100 60 100 60 100 a i il input low current (@ v il ) 25 50 25 50 25 50 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 12. input and output parameters vary 1:1 with v cc . 13. all loading with 50 to v cc . 14. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif feren- tial input signal. *typicals used for testing purposes.
NBSG16M http://onsemi.com 8 table 8. ac characteristics v cc = 0 v; v ee = ? 3.465 v to ? 2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max v outpp output voltage amplitude f in < 7 ghz (see figure 4) (note 15) f in < 10 ghz 300 200 400 250 300 200 400 250 300 100 400 150 mv t plh , t phl propagation delay to output differential 90 110 150 100 120 150 100 125 155 ps t skew duty cycle skew (note 16) 3 15 3 15 3 15 ps t jitter rms random clock jitter (note 18) f in < 10 ghz peak ? to ? peak data dependent jitter (note 19) f in < 10 gb/s 0.2 8 1 15 0.2 8 1 15 0.2 8 1.0 15 ps v inpp input voltage swing/sensitivity (differential configuration) (note 17) 75 2500 75 2500 75 2500 mv t r t f output rise/fall times @ 1 ghz q, q (20% ? 80%) 21 35 53 21 35 53 21 35 53 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 15. measured using a 400 mv source, 50% duty cycle clock source. all loading with 50 to v cc . input edge rates 40 ps (20% ? 80%). 16. see figure 5 t skew = |t plh ? t phl | for a nominal 50% differential clock input waveform. 17. v inpp(max) cannot exceed v cc ? v ee . (applicable only when v cc ? v ee < 2500 mv). input voltage swing is a single ? ended measurement operating in differential mode. 18. additive rms jitter with 50% duty cycle clock signal at 10ghz. 19. additive peak ? to ? peak data dependent jitter with nrz prbs2 31 ? 1 data rate at 10 gb/s. figure 4. output voltage amplitude (v outpp ) versus input clock frequency (f in ) at ambient temperature (typical) 0 50 100 150 200 250 300 350 400 450 500 012345678910 frequency (ghz) output voltage amplitude (mv) v cc ? v ee = 3.3 v v cc ? v ee = 2.5 v
NBSG16M http://onsemi.com 9 figure 5. ac reference measurement d d q q t phl t plh v inpp (d) = v ih (d) ? d il (d) v outpp (q) = v oh (q) ? v ol (q) v inpp (d ) = v ih (d ) ? d il (d ) v outpp (q ) = v oh (q ) ? v ol (q ) driver device receiver device qd figure 6. typical termination for output driver and device evaluation (refer to application note and8020 ? termination of ecl logic devices) q d v cc 50 50 z o = 50 z o = 50 ordering information device package shipping ? NBSG16Mmn qfn ? 16 123 units / rail NBSG16Mmng qfn ? 16 (pb ? free) 123 units / rail NBSG16Mmnr2 qfn ? 16 3000 / tape & reel NBSG16Mmnr2g qfn ? 16 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NBSG16M http://onsemi.com 10 application information all inputs can accept pecl, cml, and lvds signal levels. the input voltage can range from v cc to 1.2 v. examples interfaces are illustrated below in a 50 environment (z = 50 ). 50 v cc d d 50 sg16m v cc v td v ee v cc q 50 50 sg16m v ee figure 7. cml to cml interface z q z figure 8. lvds to cml receiver interface 50 z v cc v cc lvds driver d d 50 sg16m v ee v td v ee figure 9. pecl to cml receiver interface 50 z z v cc v cc pecl driver d d 50 sg16m v ee v bias v td v ee r t r t v ee v cc r t 5.0 v 290 3.3 v 150 2.5 v 80 recommended r t values 50 50 v td v cc v td v bias v td z
NBSG16M http://onsemi.com 11 package dimensions 16 pin qfn case 485g ? 01 issue b 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k 0.20 ??? l 0.30 0.50 exposed pad mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 NBSG16M/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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